module main(
    input   wire            clk     ,
    input   wire            rstn    ,
    input   wire            in      ,
    output  wire            out      
);

// 检测序列码10010
localparam STATE_NONE  = 3'b000,
           STATE_1     = 3'b001,
           STATE_10    = 3'b011,
           STATE_100   = 3'b010,
           STATE_1001  = 3'b110,
           STATE_10010 = 3'b111; 

reg [2:0] state, state_next;
always @(posedge clk, negedge rstn) begin 
    if(!rstn) begin 
        state <= STATE_NONE;
    end
    else begin 
        state <= state_next;
    end
end

always @(*) begin 
    case(state) 
    STATE_NONE : state_next = (in) ? STATE_1    : STATE_NONE;
    STATE_1    : state_next = (in) ? STATE_1    : STATE_10;
    STATE_10   : state_next = (in) ? STATE_1    : STATE_100;
    STATE_100  : state_next = (in) ? STATE_1001 : STATE_NONE;
    STATE_1001 : state_next = (in) ? STATE_1    : STATE_10010;
    STATE_10010: state_next = (in) ? STATE_1    : STATE_100;
    endcase
end

assign out = (state == STATE_10010);

endmodule


module tb_main();

reg [0:17] data = 18'b110010010000100101;

reg clk = 0;
always #5 clk = ~clk;

reg rstn;
reg in;
wire out;

initial begin 
    in = 0;
    rstn = 0;
    #12;
    rstn = 1;
    for(integer i=0; i<18; i=i+1) begin 
        @(negedge clk);
        in = data[i];
    end
    #10 $finish;
end

main I0(
    .clk (clk    )    ,
    .rstn(rstn   )    ,
    .in  (in     )    ,
    .out (out    )     
);

initial begin 
    $dumpfile("SeqNumDetect.vcd");
    $dumpvars(0, tb_main);
end

endmodule